The Htmt Program Execution Model

The Hybrid Technology Multi-Threaded (HTMT) Architecture has been proposed to meet the challenges of the design and development of a peta ops-level parallel architecture integrating the combined capabilities of semiconductor, superconductor, and optical technologies. This mix of technologies may yield operational attributes superior to those based solely on semiconductor technology. The HTMT architecture rede nes the relationship between memory and processors to provide e cient computation in the presence of drastically disparate cycle times and latencies. A cornerstone of the HTMT architecture is its program execution model. This paper provides an overview of the current work on the HTMT program execution model conducted at the University of Delaware. It is intended to serve as a base document which di erent HTMT groups may nd useful in their interface with the work at Delaware. The architectural concepts at Delaware are still evolving rapidly, so this paper constitutes a \work in progress" and is subject to change in the future. This paper contains: An overview of the HTMT program execution model including: (1) the thread model, (2) the memory model, and (3) thread percolation. An in-depth discussion of the runtime thread model and thread percolation. An introduction to the HTMT Operation Set. Illustration and analysis of HTMT programming using \peta-kernels." An outline of the HTMT runtime system. i